Models of on-chip transmission lines have been developed as a part of the “T-lines set” which is the core of an interconnect-aware design and modeling methodology, enabling high predictability of the critical interconnect behaviour. Further information is provided in references: Goren, D. et al., “An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 GHz) On-chip Transmission Line Approach” IEEE DATE'02 Conference, Paris March 2002, pp. 804-811 and Goren, D. et al., “On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices”, IEEE DAC'03 Conference, CA, June 2003, pp. 724-727.
During the extraction of the wire models in integrated circuits and in the modeling of on-chip transmission lines, it is necessary to calculate the static capacitance of the interconnect structures.
There have been numerous prior solutions to this problem. The most common solution is to build a database of solutions (a look-up table) using a numerical electromagnetic solver, and then to interpolate between these solutions using polynomial functions.
The drawbacks of this prior art solution are as follows.
1) The interpolation is quite approximate, and its validity is severely limited to the range of geometries used in the numerical database. As a special case of this, polynomial interpolations fail to give the correct asymptotic results for the extreme cases (very wide line, very thick line, etc.).
2) It is very time consuming to build and run the numerical database repeatedly when using the models for a different silicon chip technology with different wire cross sectional dimensions and often with multiple metal stack options.
In addition to this, there have been several efforts in the past to develop expressions for the capacitance in the common cases of VLSI designs (Very Large Scale Integration designs). The main drawback of these solutions is that they are not physics based, and rather use several known functions (such as logarithmic functions, power functions, etc.) which limits their range of applicability.
Semi-analytical modeling is a very cost-effective method, compared with both the lookup table method and the numerical simulation method. The semi-analytical method is a method which uses closed form explicit expressions whose result approximates the exact result.
A semi-analytic solution is disclosed in Lei He, “Modeling and Optimization for VLSI Layout”, UCLA, Microsoft PowerPoint 1997. However, this solution lacks flexibility since it is restricted to some specific cases and cannot be simply extended to include other structures.
Only in few restricted cases it is possible to get the analytical solution (for example, W. H. Chang, “Analytical IC Metal-Line Capacitance Formulas.” IEEE Transactions on Microwave Theory and Techniques, September 1976, pp. 608-611 for single signal line without side shields) which results in much more complicated expressions compared with a semi-analytical approach.
An aim of the present invention is to provide capacitance modeling using semi-analytical methods which can be applied to a range of different structures.
The proposed method has the advantage over other semi-analytical methods, in that it is not based on arbitrary functions (such as power functions, logarithm functions, etc) which are usually generated to approximate the real behavior. The proposed method is based on a field lines approach which is built on physics-based approximations for electric field lines from which the resulting expressions are formally derived.
The proposed method introduces a set of semi-analytical formulations for 2D modeling of typical on-chip interconnect line structures. The method may be applied to on-chip interconnect wire structures including the consideration of the crossing lines effect which are modeled as a solid metal plane layer. This set of interconnect lines covers most typical needs of both VLSI designs and typical RF designs. These explicit expressions can be used both for the modeling of selected critical lines, or as part of a post layout RC extraction tool.
The proposed method solves the problem of calculating the static capacitance matrix for the main common cases found in typical VLSI chip designs.